Field of the Invention
The invention relates to a method for producing an electrical connection between front and rear sides of semiconductor chips.
In certain integrated circuits or semiconductor chips, the substrate has to be connected to a predetermined reference-ground potential (e.g. ground) for the functionality of the circuit. This is usually done by connecting the rear side of the chip, that is to say a substrate side, to the reference-ground potential.
When housing semiconductor chips, this can be done by making contact with the rear side of the chip using a module terminal provided for this purpose. When the semiconductor chip is applied to a lead frame, the rear side of the semiconductor chip is connected directly to a metal area of the lead frame. The metal area may in turn be contact-connected to a module terminal connected to the predetermined reference-ground potential during operation of the circuit, or, internally in the housing, to a terminal or pad connected to the predetermined reference-ground potential. What is essential in this case is that contact be made with the rear side of the chip in the process of housing the semiconductor chip.
However, when the semiconductor chip is mounted without a housing, for example by being bonded to a printed circuit board, other methods are required for making contact with the rear side of the chip.
In the case of so-called flip-chip technology, in particular, only rewiring configurations and a solder ball structure are provided on the front side of the chip, that is to say the chip surface. In this case, the semiconductor chip is placed with the front side of the chip facing down (which explains the expression xe2x80x9cflip-chipxe2x80x9d) on a substrate which, similarly to a printed circuit board, has a wiring structure for connecting the semiconductor chips to be mounted on the substrate, and is electrically connected to the substrate by heating the solder balls. The rear side of the chip, which is now uncovered, has to be connected separately to the reference-ground potential. This can be done for example by reverse contact-making from the rear side of the chip to the front side of the chip.
It is accordingly an object of the invention to provide a method for producing an electrical connection between the front and rear sides of semiconductor chips which overcomes the above-mentioned disadvantages of the prior art devices of this general type, which enables a reliable electrical connection of front and rear sides of the semiconductor chips in a simple manner.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for producing electrical connections. The method includes providing a wafer; applying a sheet defining separating lines on a rear side of the wafer; and dividing the wafer along the separating lines into semiconductor chips each having a front side and a rear side. A metal nucleating-agent layer is applied in a region of the separating lines at least in sections onto a front side of the wafer and also on an edge region, contiguous therewith, of the semiconductor chips. The metal nucleating-agent layer is then irradiated to produce metal nuclei on a surface of the metal nucleating-agent layer. At least one interconnect is formed which is contiguous on the front side and the edge region and extends as far as the rear side of the semiconductor chips, by chemical metallization on an irradiated section of the surface of the metal nucleating-agent layer of each of the semiconductor chips.
In accordance with an added feature of the invention, there are the steps of providing the sheet with perforations for applying the metal nucleating-agent layer on the rear side of the semiconductor chips in the region of the separating lines; and covering the rear side of the semiconductor chips, at least in sections, with the metal nucleating-agent layer.
Published, Non-Prosecuted German Patent Application DE 197 313 46 discloses a method for producing interconnect structures on a non-conductive carrier material. In this method, a metal nucleating-agent layer containing heavy metal complexes is applied to a non-conductive carrier material. For this purpose, the layer material contains microporous or microrough carrier particles to which organic, non-conductive heavy metal complexes are bound. In the region of interconnect structures to be produced, the metal nucleating-agent layer is irradiated with electromagnetic radiation in the UV range, as a result of which heavy-metal nuclei are liberated. The carrier particles are uncovered by ablation and the heavy-metal nuclei are liberated by the bound heavy metal complex being broken open. The irradiated region is subsequently metallized chemically-reductively in order to form interconnect structures. An essential concept of the invention is the adaptation of the method disclosed in the German Patent Application DE 197 313 46 A1 for chip rear-side and front-side connection still during the wafer process and the German Patent Application DE 197 314 46 A1 is hereby incorporated by reference.
According to the invention, in particular after the wafer has been sawn into semiconductor chips, which are still situated on the sawing sheet, the metal nucleating-agent layer, in particular a photosensitive resist, is applied at least in sections onto the front side and also the edges of the semiconductor chips.
In the region of interconnects to be produced for the front-/rear-side reverse contact-making of the semiconductor chips, heavy-metal nuclei are formed in the heavy-metal-containing layer by irradiation. Electrically conductive regions are then formed on the heavy-metal nuclei layers by chemical metallization, which regions extend at least partly from the front side over the edges as far as the rear side of the semiconductor chips. The regions abut a metallized rear side and form electrical connections from the front side to the rear side of the semiconductor chips.
One advantage of the method is to be seen in the fact that it is possible, in a reliable and simple manner, to form well-adhering interconnects for making contact with the front and rear sides of a semiconductor chip during the process for producing the semiconductor chips. As a result, the rear side, that is to say the substrate side, of the semiconductor chips is electrically connected to the front side, and making contact with the rear side separately in a subsequent production step, for example during the housing process, is obviated. Therefore, this method is especially suitable for mounting the semiconductor chips without a housing or for xe2x80x9cflip-chipxe2x80x9d technology.
In order to obtain a particularly reliable electrical connection between the front and rear sides of the semiconductor chips, the rear side is preferably also covered at least partly with the metal nucleating-agent layer and the further method steps are also applied to these rear-side regions. This produces wiring configurations between the front and rear sides of the semiconductor chips which cover parts both of the front side and of the rear side of the semiconductor chips and reliably make contact with the latter.
In accordance with an additional feature of the invention, there is the step of providing the metal nucleating-agent layer with one of microporous and microrough carrier particles in a uniform distribution, the metal nuclei form on a surface of the carrier particles in the irradiating step.
In accordance with another feature of the invention, there is the step of applying the metal nucleating-agent layer using wafer-scale printing technology.
In accordance with a further feature of the invention, there is the step of providing the metal nucleating-agent layer with an organic non-conductive heavy-metal complex.
The metal nucleating-agent layer is preferably applied essentially in the region of the separating lines (sawing lines) of the wafer between the semiconductor chips. In a particularly preferred manner, the metal nucleating-agent layer essentially covers the corners of the semiconductor chips. Particularly when using wafer-scale printing technology to apply the heavy-metal-containing layer, it is advantageous to apply the metal nucleating-agent layer only in the above-mentioned regions, in order, on the one hand, to save material and, on the other hand, to avoid additional steps for producing layer sections that are not necessary for the reverse contact-making.
The application of the metal nucleating layer on the rear side of the wafer or the semiconductor chips is made more difficult by the sawing sheet, however, so that the sheet is preferably perforated on the rear side of the semiconductor chips. Perforation of the sawing sheet is provided in particular in the region of the sawing lines and of the corners of the semiconductor chips. The metal nucleating-agent layer is especially applied, for example printed or sprayed, in the form of circular regions onto the points of intersection of the sawing line. One circular region of the metal nucleating-agent layer at a point of intersection of two sawing lines advantageously covers four semiconductor chips, that is to say the corners of four different semiconductor chips, with the result that a rear side connection for the semiconductor chips of a wafer can be produced by this process in a simple manner merely using relatively few perforations or regions of the heavy-metal-containing layer.
The metal nucleating-agent layer preferably has palladium or palladium compounds in complex form. These require, for initiating structuring cleavage reactions, irradiation with a significantly lower energy density than other heavy-metal compounds.
The targeted irradiation is preferably effected by a mask aligner or stepper. The mask aligner or stepper operates with UV radiation that liberates palladium or palladium compounds on the surface of the layer for the formation of palladium nuclei layers. Mask aligners or steppers are used in semiconductor technology for exposing the wafers with the structures predetermined by exposure masks. This enables the method according to the invention to be incorporated in a simple manner in the method sequence or process sequence for producing integrated circuits, for example by providing a special mask for exposing the heavy-metal-containing layers.
The light radiation may preferably be produced by a laser (especially a KrF excimer laser where xcex=248 nm), the small beam diameter of which enables particularly fine interconnects or electrical connections to be formed. Furthermore, the high radiation intensity of the laser affords the advantage that the heavy-metal layer only has to be irradiated very briefly in order to form heavy-metal nuclei layers.
In the chip composite, that is to say when the semiconductor chips are still bonded on the sawing sheet, it is possible to bore into the layer in a targeted manner during the targeted irradiation by a laser by increasing the radiation intensity (focussing) thereof. Since the unfocussed laser radiation used for surface activation only penetrates the layer surface, this is necessary for forming vertical heavy-metal nuclei layers on the edges of the semiconductor chips. In the region of the sawing lines, this enables the vertical nucleation, that is to say formation of heavy-metal nuclei layers along the chip edges. On account of the focussing, the laser radiation penetrates deeply into the layer at the boring location and nucleates the edges of the bored hole. Consequently, the interconnect can xe2x80x9cgrowxe2x80x9d into the bored hole during subsequent metallization.
The method according to the invention also makes it possible to produce rewiring configurations of individual interconnects from the pads to the rear side of the chip. This is advantageous in particular for stacking the semiconductor chips to form multichip modules or for memory stacking (chip stacking).
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for producing an electrical connection between the front and rear sides of semiconductor chips, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.